Career Evolutions is searching for quality ASIC Designer s for a $7.5B global company with over 90,000 employees in 31 countries. We have multiple immediate vacancies now open in San Jose, CA! The position is an 8 to 12 month contract with hourly pay rate of $55 - $70. Relocation and a great benefit package available!
Required Technical Skills & Competencies: ASIC Designers with good Verilog / VHDL skills along with RTL design, static timing analysis (STA) and EDA design tools experience, e.g. – Synopsys / Mentor Graphics tools OK.
You must have demonstrable experience, of having been in multiple full life-cycle projects, from spec to tape-outs. Overall at least 3 to 5 years’ experience of verifiable industrial exp.
